1. Field of the Invention
The present invention relates generally to analog-to-digital converters (ADCs) and more particularly to folding amplifiers.
2. Description of the Related Art
Single-bit ADCs quantize an analog input signal to a digital output signal that consists of one binary bit. Although useful in themselves, they also serve as building blocks for constructing more complex ADC structures (e.g., serial ADCs and subranging ADCs) in which they are typically positioned in a serial arrangement of ADC stages. The terminal ADC in such an arrangement can generally be a simple comparator but preceding stages must process the input analog signal and pass it to successive stages for further quantization.
An exemplary preceding single-bit stage comprises an amplifier, a subtracter and a comparator that drives a single-bit digital-to-analog converter (DAC) in the form of a switch. The amplifier and the comparator are coupled to the analog input signal and the output of the single-bit DAC is subtracted from the amplifier's output signal in the subtracter to produce a residue analog signal that is passed to a successive ADC stage.
For one polarity of the input signal, the residue signal equals the amplified input signal less a first analog signal from the DAC. For the other polarity of the input signal, the residue signal equals the amplified input signal less a second analog signal from the DAC.
Accordingly, the residue signal contains two linear regions separated by a discontinuity equal to the difference between the first and second analog signals. The discontinuity occurs at the input signal's polarity transition. The gain of the amplifier is typically configured with a gain of two so as to maintain a constant signal range between the input and output. However, successful operation of a serial arrangement of these single-bit stages is significantly degraded by transients that are generated by each stage's discontinuity.
The discontinuity and resultant transient production of the foregoing single-bit structure are avoided by substitution of folding amplifiers which have a positive gain for one polarity of input signal and a negative gain for the other polarity. The output signal is generally level-shifted to facilitate signal quantization in a successive folding amplifier.
An exemplary unity-gain folding amplifier is disclosed in U.S. Pat. No. 5,550,492 issued Aug. 27, 1996 to Frank Murden and assigned to Analog Devices, Inc., the assignee of the present invention. This amplifier includes complimentary differential pairs of transistors which perform the folding process and current sources which are coupled through respective resistors to respective differential pairs to perform the level-shifting process.
Because of its simplicity and because the input signal is only processed through current conversion structures (i.e., base-emitter junctions), this folding amplifier is generally smaller, less expensive, more efficient and faster than adjustable-gain folding amplifier structures. The unity gain of this structure, however, causes its output signal range to be halved from its input signal range. When necessary, therefore, to keep the signal range above an operational limit, one or more initial stages of a serial arrangement of ADC stages can be formed with the adjustable-gain folding amplifier structures.
However, any linearity degradation of this unity-gain folding amplifier prevents a full realization of its advantages because such degradation complicates quantization in successive stages and limits the number of unity-gain folding amplifier that can be reliably operated in a serial arrangement.